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000874666 1001_ $$0P:(DE-Juel1)173033$$aLiu, Mingshan$$b0$$eCorresponding author
000874666 245__ $$aVertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm
000874666 260__ $$aNew York, NY$$bIEEE$$c2020
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000874666 520__ $$aIn this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
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000874666 7001_ $$0P:(DE-HGF)0$$aScholz, Stefan$$b1
000874666 7001_ $$0P:(DE-Juel1)165704$$aHardtdegen, Alexander$$b2
000874666 7001_ $$0P:(DE-Juel1)177006$$aBae, Jin Hee$$b3
000874666 7001_ $$0P:(DE-HGF)0$$aHartmann, Jean-Michel$$b4
000874666 7001_ $$0P:(DE-HGF)0$$aKnoch, Joachim$$b5
000874666 7001_ $$0P:(DE-Juel1)125588$$aGrutzmacher, Detlev$$b6$$ufzj
000874666 7001_ $$0P:(DE-Juel1)125569$$aBuca, Dan$$b7$$ufzj
000874666 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b8
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