TY  - JOUR
AU  - Liu, Mingshan
AU  - Scholz, Stefan
AU  - Hardtdegen, Alexander
AU  - Bae, Jin Hee
AU  - Hartmann, Jean-Michel
AU  - Knoch, Joachim
AU  - Grutzmacher, Detlev
AU  - Buca, Dan
AU  - Zhao, Qing-Tai
TI  - Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm
JO  - IEEE electron device letters
VL  - 41
IS  - 4
SN  - 1558-0563
CY  - New York, NY
PB  - IEEE
M1  - FZJ-2020-01582
SP  - 533 - 536
PY  - 2020
AB  - In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000522206300002
DO  - DOI:10.1109/LED.2020.2971034
UR  - https://juser.fz-juelich.de/record/874666
ER  -