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@ARTICLE{Liu:874666,
      author       = {Liu, Mingshan and Scholz, Stefan and Hardtdegen, Alexander
                      and Bae, Jin Hee and Hartmann, Jean-Michel and Knoch,
                      Joachim and Grutzmacher, Detlev and Buca, Dan and Zhao,
                      Qing-Tai},
      title        = {{V}ertical {G}e {G}ate-{A}ll-{A}round {N}anowire p{MOSFET}s
                      {W}ith a {D}iameter {D}own to 20 nm},
      journal      = {IEEE electron device letters},
      volume       = {41},
      number       = {4},
      issn         = {1558-0563},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {FZJ-2020-01582},
      pages        = {533 - 536},
      year         = {2020},
      abstract     = {In this work, we demonstrate vertical Ge gate-all-around
                      (GAA) nanowire pMOSFETs fabricated with a CMOS compatible
                      top-down approach. Vertical Ge nanowires with diameters down
                      to 20 nm and an aspect ratio of ~11 were achieved by
                      optimized Cl 2 -based dry etching and self-limiting digital
                      etching. Employing a GAA architecture, post-oxidation
                      passivation and NiGe contacts, high performance Ge nanowire
                      pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V
                      and a high $\text {I}_{ \mathrm{\scriptscriptstyle
                      ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of
                      ${2.1}\times {10}^{{6}}$ . The electrical behavior was also
                      studied with temperature-dependent measurements. The
                      deviation between the experimental SS and the ideal kT/q
                      $\cdot $ ln10 values stems from the density of interface
                      traps $(\text {D}_{\text {it}})$ . Our measurements suggest
                      that lowering the top contact resistance is a key to further
                      performance improvement of vertical Ge GAA nanowire
                      transistors.},
      cin          = {PGI-9 / JARA-FIT / PGI-7},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-9-20110106 / I:(DE-Juel1)VDB881 /
                      I:(DE-Juel1)PGI-7-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000522206300002},
      doi          = {10.1109/LED.2020.2971034},
      url          = {https://juser.fz-juelich.de/record/874666},
}