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001     874666
005     20210130004739.0
024 7 _ |a 10.1109/LED.2020.2971034
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024 7 _ |a 0741-3106
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100 1 _ |a Liu, Mingshan
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245 _ _ |a Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm
260 _ _ |a New York, NY
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520 _ _ |a In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
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700 1 _ |a Scholz, Stefan
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700 1 _ |a Hardtdegen, Alexander
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700 1 _ |a Bae, Jin Hee
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700 1 _ |a Hartmann, Jean-Michel
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700 1 _ |a Knoch, Joachim
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700 1 _ |a Grutzmacher, Detlev
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700 1 _ |a Buca, Dan
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700 1 _ |a Zhao, Qing-Tai
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773 _ _ |a 10.1109/LED.2020.2971034
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