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| Hauptseite > Externe Publikationen > Vita Publikationen > Study of SEU effects in circuits developed in 110 nm CMOS technology |
| Hauptseite > Externe Publikationen > Vita Publikationen > Study of SEU effects in circuits developed in 110 nm CMOS technology |
| Contribution to a conference proceedings/Contribution to a book | FZJ-2020-04553 |
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2020
Sissa Medialab Trieste, Italy
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Please use a persistent id in citations: doi:10.22323/1.370.0126
Abstract: Channel configuration registers of a full size prototype for the custom readout circuit of silicon double-sided microstrips of PANDA Micro Vertex Detector were tested for upset effects. The ASIC is developed in a commercial 110 nm CMOS technology and implements both Triple Modular Redundancy and Hamming Encoding techniques. Results from tests with ion and proton beams show the robustness level of these two techniques against the upset effects and allow the evaluation of that commercial 110 nm technology in the PANDA experiment.
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