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@INPROCEEDINGS{Vliex:894628,
      author       = {Vliex, Patrick and Nielinger, Dennis and Artanov, Anton and
                      Degenhardt, Carsten and Grewing, Christian and Kruth, Andre
                      and van Waasen, Stefan},
      title        = {{S}calable {Q}uantum {B}it {C}ontrol ({SQ}u{B}i{C}1)
                      {C}ryogenic {CMOS} {IC} for {S}pin {Q}ubit {C}ontrol},
      reportid     = {FZJ-2021-03325},
      year         = {2021},
      abstract     = {The Central Institute for Electronic Systems at
                      Forschungszentrum Jülich develops, designs and tests
                      scalable solutionsfor the control, readout and writing of
                      qubits to be used in future quantum computers. The focus
                      lies on highly integratedsystem-on-chip (SoC) solutions.One
                      of the main challenges to integrate a high number of qubits
                      is their connection to the control electronics at
                      roomtemperature and their sensitivity to noise [1,2].
                      Therefore, close proximity of the integrated control
                      circuits to the qubitspromises significant benefits and will
                      most likely be the only way to reach qubit numbers beyond a
                      thousand, thus gainingincreased attention in the last years
                      [3-5].The operation of GaAs qubits requires voltage pulses,
                      whereas SiGe qubits are controlled by high frequency RF
                      signals.Multiple DC voltages are required to form potential
                      wells and tune the qubit into operating region for both
                      types of qubits. Atest chip was designed and layouted in a
                      commercial 65nm CMOS process [6] to fill this role. The chip
                      employs a 20 GHzvoltage controlled oscillator (VCO) to
                      generate RF signals for future use in a cryogenic
                      Phase-Locked-Loop (PLL), enablingSiGe qubit control. A 250
                      MS/s pulse DAC for operation of GaAs qubits is realized on
                      the chip. A low power multi-outputchanneldigital-to-analog
                      converter is included togenerate DC bias voltages, among
                      other additional circuitry forperformance verification,
                      operational amplifiers are includedin order to cope with the
                      low driving strength of the DAC. Forthe on-chip clock
                      generation a digital controlled oscillator (DCO) operating
                      in the 100-500 MHz range is used. The chip isdesigned to be
                      placed in close proximity to the qubit at the millikelvin
                      temperature stageto generate the DC and pulsevoltagesand on
                      the 4K-stage for RF signal generation(VCO).In this
                      presentation, we will describe the chip architecture in
                      detailandshow measured chip performance at
                      cryogenictemperature below 10 K.[1]C. G. Almudever et al.,
                      "The engineering challenges in quantum computing," Design,
                      Automation $\&$ Test in EuropeConference $\&$ Exhibition
                      (DATE), 2017, Lausanne, 2017, pp. 836-845.[2]L.M.K.
                      Vandersypen, H. Bluhm et al., "Interfacing spin qubits in
                      quantum dots and donors: hot dense and coherent", npjQuantum
                      Information, vol. 3, no. 1, pp. 34, Sep. 2017.[3]B. Patra et
                      al., "Cryo-CMOS Circuits and Systems for Quantum Computing
                      Applications," in IEEE Journal of Solid-StateCircuits, vol.
                      53, no. 1, pp. 309-321, Jan. 2018.[4]C. Degenhardt et al.,
                      “CMOS based scalable cryogenic Control Electronics for
                      Qubits,” InternationalConference onRebooting Computing
                      (ICRC), Washington, Dec 2017[5]A. Beckers, F. Jazaeri, H.
                      Bohuslavskyi, L. Hutin, S. De Franceschi and C. Enz,
                      "Design-oriented modeling of 28 nmFDSOI CMOS technology down
                      to 4.2 K for quantum computing," 2018 Joint International
                      EUROSOI Workshop andInternational Conference on Ultimate
                      Integration on Silicon (EUROSOI-ULIS), Granada, 2018, pp.
                      1-4.[6]C. Degenhardt et al., "Systems Engineering of
                      Cryogenic CMOS Electronics for Scalable Quantum Computers,"
                      2019IEEE International Symposium on Circuits and Systems
                      (ISCAS), Sapporo, Japan, 2019, pp. 1-5.},
      month         = {Apr},
      date          = {2021-04-12},
      organization  = {IEEE 14th Workshop on Low Temperature
                       Electronics, Virtual (Italy), 12 Apr
                       2021 - 16 Apr 2021},
      subtyp        = {Invited},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5223 - Quantum-Computer Control Systems and Cryoelectronics
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5223},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/894628},
}