TY  - CONF
AU  - Zaourar, Lilia
AU  - Benazouz, Mohammed
AU  - Mouhagir, Ayoub
AU  - Jebali, Fatma
AU  - Sassolas, Tanguy
AU  - Weill, Jean-Christophe
AU  - Falquez, Carlos
AU  - Ho, Nam
AU  - Pleiter, Dirk
AU  - Portero, Antonio
AU  - Suarez, Estela
AU  - Petrakis, Polydoros
AU  - Papaefstathiou, Vassilis
AU  - Marazakis, Manolis
AU  - Radulovic, Milan
AU  - Martinez, Francesc
AU  - Armejach, Adria
AU  - Casas, Marc
AU  - Nocua, Alejandro
AU  - Dolbeau, Romain
TI  - Multilevel simulation-based co-design of next generation HPC microprocessors
M1  - FZJ-2021-04744
SP  - 12 p.
PY  - 2021
AB  - This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings.We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor.Thus, we provide critical insights for efficient design of future HPC microprocessors.
T2  - The 12th International Workshop on Performance Modeling, Benchmarking and Simulation of High-Performance Computer Systems
CY  - 15 Nov 2021 - 15 Nov 2021, St. Louis (USA)
Y2  - 15 Nov 2021 - 15 Nov 2021
M2  - St. Louis, USA
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
UR  - https://juser.fz-juelich.de/record/903015
ER  -