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@INPROCEEDINGS{Zaourar:903015,
      author       = {Zaourar, Lilia and Benazouz, Mohammed and Mouhagir, Ayoub
                      and Jebali, Fatma and Sassolas, Tanguy and Weill,
                      Jean-Christophe and Falquez, Carlos and Ho, Nam and Pleiter,
                      Dirk and Portero, Antonio and Suarez, Estela and Petrakis,
                      Polydoros and Papaefstathiou, Vassilis and Marazakis,
                      Manolis and Radulovic, Milan and Martinez, Francesc and
                      Armejach, Adria and Casas, Marc and Nocua, Alejandro and
                      Dolbeau, Romain},
      title        = {{M}ultilevel simulation-based co-design of next generation
                      {HPC} microprocessors},
      reportid     = {FZJ-2021-04744},
      pages        = {12 p.},
      year         = {2021},
      comment      = {SC workshop proceedings},
      booktitle     = {SC workshop proceedings},
      abstract     = {This paper demonstrates the combined use of three
                      simulation tools in support of a co-design methodology for
                      an HPC-focused System-on-a-Chip (SoC) design. The simulation
                      tools make different trade-offs between simulation speed,
                      accuracy and model abstraction level, and are shown to be
                      complementary. We apply the MUSA trace-based simulator for
                      the initial sizing of vector register length, system-level
                      cache (SLC) size and memory bandwidth. It has proven to be
                      very efficient at pruning the design space, as its models
                      enable sufficient accuracy without having to resort to
                      highly detailed simulations. Then we apply gem5, a
                      cycle-accurate micro-architecture simulator, for a more
                      refined analysis of the performance potential of our
                      reference SoC architecture, with models able to capture
                      detailed hardware behavior at the cost of simulation speed.
                      Furthermore, we study the network-on-chip (NoC) topology and
                      IP placements using both gem5 for representative small- to
                      medium-scale configurations and SESAM/VPSim, a
                      transaction-level emulator for larger scale systems with
                      good simulation speed and sufficient architectural details.
                      Overall, we consider several system design concerns, such as
                      processor subsystem sizing and NoC settings.We apply the
                      selected simulation tools, focusing on different levels of
                      abstraction, to study several configurations with various
                      design concerns and evaluate them to guide architectural
                      design and optimization decisions. Performance analysis is
                      carried out with a number of representative benchmarks. The
                      obtained numerical results provide guidance and hints to
                      designers regarding SIMD instruction width, SLC sizing,
                      memory bandwidth as well as the best placement of memory
                      controllers and NoC form factor.Thus, we provide critical
                      insights for efficient design of future HPC
                      microprocessors.},
      month         = {Nov},
      date          = {2021-11-15},
      organization  = {The 12th International Workshop on
                       Performance Modeling, Benchmarking and
                       Simulation of High-Performance Computer
                       Systems, St. Louis (USA), 15 Nov 2021 -
                       15 Nov 2021},
      cin          = {JSC},
      cid          = {I:(DE-Juel1)JSC-20090406},
      pnm          = {5122 - Future Computing $\&$ Big Data Systems (POF4-512) /
                      EPI SGA1 - SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN
                      PROCESSOR INITIATIVE (EPI) (826647)},
      pid          = {G:(DE-HGF)POF4-5122 / G:(EU-Grant)826647},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      url          = {https://juser.fz-juelich.de/record/903015},
}