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| Hauptseite > Publikationsdatenbank > Multilevel simulation-based co-design of next generation HPC microprocessors > print |
| Hauptseite > Publikationsdatenbank > Multilevel simulation-based co-design of next generation HPC microprocessors > print |
| 001 | 903015 | ||
| 005 | 20220502144611.0 | ||
| 024 | 7 | _ | |a 2128/29249 |2 Handle |
| 037 | _ | _ | |a FZJ-2021-04744 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Zaourar, Lilia |0 P:(DE-HGF)0 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a The 12th International Workshop on Performance Modeling, Benchmarking and Simulation of High-Performance Computer Systems |g PMBS21 |c St. Louis |d 2021-11-15 - 2021-11-15 |w USA |
| 245 | _ | _ | |a Multilevel simulation-based co-design of next generation HPC microprocessors |
| 260 | _ | _ | |c 2021 |
| 295 | 1 | 0 | |a SC workshop proceedings |
| 300 | _ | _ | |a 12 p. |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
| 336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1651488464_14420 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
| 520 | _ | _ | |a This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings.We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor.Thus, we provide critical insights for efficient design of future HPC microprocessors. |
| 536 | _ | _ | |a 5122 - Future Computing & Big Data Systems (POF4-512) |0 G:(DE-HGF)POF4-5122 |c POF4-512 |f POF IV |x 0 |
| 536 | _ | _ | |a EPI SGA1 - SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI) (826647) |0 G:(EU-Grant)826647 |c 826647 |f H2020-SGA-LPMT-2018 |x 1 |
| 700 | 1 | _ | |a Benazouz, Mohammed |0 P:(DE-HGF)0 |b 1 |
| 700 | 1 | _ | |a Mouhagir, Ayoub |0 P:(DE-HGF)0 |b 2 |
| 700 | 1 | _ | |a Jebali, Fatma |0 P:(DE-HGF)0 |b 3 |
| 700 | 1 | _ | |a Sassolas, Tanguy |0 P:(DE-HGF)0 |b 4 |
| 700 | 1 | _ | |a Weill, Jean-Christophe |0 P:(DE-HGF)0 |b 5 |
| 700 | 1 | _ | |a Falquez, Carlos |0 P:(DE-Juel1)179531 |b 6 |
| 700 | 1 | _ | |a Ho, Nam |0 P:(DE-Juel1)176469 |b 7 |
| 700 | 1 | _ | |a Pleiter, Dirk |0 P:(DE-Juel1)144441 |b 8 |
| 700 | 1 | _ | |a Portero, Antonio |0 P:(DE-Juel1)177768 |b 9 |
| 700 | 1 | _ | |a Suarez, Estela |0 P:(DE-Juel1)142361 |b 10 |
| 700 | 1 | _ | |a Petrakis, Polydoros |0 P:(DE-HGF)0 |b 11 |
| 700 | 1 | _ | |a Papaefstathiou, Vassilis |0 P:(DE-HGF)0 |b 12 |
| 700 | 1 | _ | |a Marazakis, Manolis |0 P:(DE-HGF)0 |b 13 |
| 700 | 1 | _ | |a Radulovic, Milan |0 P:(DE-HGF)0 |b 14 |
| 700 | 1 | _ | |a Martinez, Francesc |0 P:(DE-HGF)0 |b 15 |
| 700 | 1 | _ | |a Armejach, Adria |0 P:(DE-HGF)0 |b 16 |
| 700 | 1 | _ | |a Casas, Marc |0 P:(DE-HGF)0 |b 17 |
| 700 | 1 | _ | |a Nocua, Alejandro |0 P:(DE-HGF)0 |b 18 |
| 700 | 1 | _ | |a Dolbeau, Romain |0 P:(DE-HGF)0 |b 19 |
| 773 | _ | _ | |y 2021 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/903015/files/Zaourar_PMBS_SC21_codesign.pdf |y OpenAccess |
| 909 | C | O | |o oai:juser.fz-juelich.de:903015 |p openaire |p open_access |p driver |p VDB |p ec_fundedresources |p dnbdelivery |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 0 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 1 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 2 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 3 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 4 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a CEA |0 I:(DE-HGF)0 |b 5 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 6 |6 P:(DE-Juel1)179531 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 7 |6 P:(DE-Juel1)176469 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 8 |6 P:(DE-Juel1)144441 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 9 |6 P:(DE-Juel1)177768 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 10 |6 P:(DE-Juel1)142361 |
| 910 | 1 | _ | |a Forth |0 I:(DE-HGF)0 |b 11 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a Forth |0 I:(DE-HGF)0 |b 12 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a Forth |0 I:(DE-HGF)0 |b 13 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a BSC |0 I:(DE-HGF)0 |b 14 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a BSC |0 I:(DE-HGF)0 |b 15 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a BSC |0 I:(DE-HGF)0 |b 16 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a BSC |0 I:(DE-HGF)0 |b 17 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a BSC |0 I:(DE-HGF)0 |b 18 |6 P:(DE-HGF)0 |
| 910 | 1 | _ | |a SiPearl |0 I:(DE-HGF)0 |b 19 |6 P:(DE-HGF)0 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Engineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action |1 G:(DE-HGF)POF4-510 |0 G:(DE-HGF)POF4-512 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Supercomputing & Big Data Infrastructures |9 G:(DE-HGF)POF4-5122 |x 0 |
| 914 | 1 | _ | |y 2021 |
| 915 | _ | _ | |a OpenAccess |0 StatID:(DE-HGF)0510 |2 StatID |
| 920 | 1 | _ | |0 I:(DE-Juel1)JSC-20090406 |k JSC |l Jülich Supercomputing Center |x 0 |
| 980 | _ | _ | |a contrib |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a contb |
| 980 | _ | _ | |a I:(DE-Juel1)JSC-20090406 |
| 980 | _ | _ | |a UNRESTRICTED |
| 980 | 1 | _ | |a FullTexts |
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