% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@ARTICLE{Heittmann:906315,
      author       = {Heittmann, Arne and Psychou, Georgia and Trensch, Guido and
                      Cox, Charles E. and Wilcke, Winfried W. and Diesmann, Markus
                      and Noll, Tobias G.},
      title        = {{S}imulating the {C}ortical {M}icrocircuit {S}ignificantly
                      {F}aster {T}han {R}eal {T}ime on the {IBM} {INC}-3000
                      {N}eural {S}upercomputer},
      journal      = {Frontiers in neuroscience},
      volume       = {15},
      issn         = {1662-453X},
      address      = {Lausanne},
      publisher    = {Frontiers Research Foundation},
      reportid     = {FZJ-2022-01365},
      pages        = {728460},
      year         = {2022},
      abstract     = {This article employs the new IBM INC-3000 prototype
                      FPGA-based neural supercomputer to implement a widely used
                      model of the cortical microcircuit. With approximately
                      80,000 neurons and 300 Million synapses this model has
                      become a benchmark network for comparing simulation
                      architectures with regard to performance. To the best of our
                      knowledge, the achieved speed-up factor is 2.4 times larger
                      than the highest speed-up factor reported in the literature
                      and four times larger than biological real time
                      demonstrating the potential of FPGA systems for neural
                      modeling. The work was performed at Jülich Research Centre
                      in Germany and the INC-3000 was built at the IBM Almaden
                      Research Center in San Jose, CA, United States. For the
                      simulation of the microcircuit only the programmable logic
                      part of the FPGA nodes are used. All arithmetic is
                      implemented with single-floating point precision. The
                      original microcircuit network with linear LIF neurons and
                      current-based exponential-decay-, alpha-function- as well as
                      beta-function-shaped synapses was simulated using exact
                      exponential integration as ODE solver method. In order to
                      demonstrate the flexibility of the approach, additionally
                      networks with non-linear neuron models (AdEx, Izhikevich)
                      and conductance-based synapses were simulated, applying
                      Runge–Kutta and Parker–Sochacki solver methods. In all
                      cases, the simulation-time speed-up factor did not decrease
                      by more than a very few percent. It finally turns out that
                      the speed-up factor is essentially limited by the latency of
                      the INC-3000 communication system.},
      cin          = {PGI-10 / INM-6 / INM-10 / IAS-6 / JSC},
      ddc          = {610},
      cid          = {I:(DE-Juel1)PGI-10-20170113 / I:(DE-Juel1)INM-6-20090406 /
                      I:(DE-Juel1)INM-10-20170113 / I:(DE-Juel1)IAS-6-20130828 /
                      I:(DE-Juel1)JSC-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / Advanced
                      Computing Architectures $(aca_20190115)$ / 5122 - Future
                      Computing $\&$ Big Data Systems (POF4-512) / 5111 -
                      Domain-Specific Simulation $\&$ Data Life Cycle Labs (SDLs)
                      and Research Groups (POF4-511)},
      pid          = {G:(DE-HGF)POF4-5234 / $G:(DE-Juel1)aca_20190115$ /
                      G:(DE-HGF)POF4-5122 / G:(DE-HGF)POF4-5111},
      typ          = {PUB:(DE-HGF)16},
      pubmed       = {pmid:35126034},
      UT           = {WOS:000750070900001},
      doi          = {10.3389/fnins.2021.728460},
      url          = {https://juser.fz-juelich.de/record/906315},
}