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@ARTICLE{Hilder:907016,
      author       = {Hilder, J. and Pijn, D. and Onishchenko, O. and Stahl, A.
                      and Orth, M. and Lekitsch, B. and Rodriguez-Blanco, A. and
                      Müller, M. and Schmidt-Kaler, F. and Poschinger, U. G.},
      title        = {{F}ault-{T}olerant {P}arity {R}eadout on a
                      {S}huttling-{B}ased {T}rapped-{I}on {Q}uantum {C}omputer},
      journal      = {Physical review / X},
      volume       = {12},
      number       = {1},
      issn         = {2160-3308},
      address      = {College Park, Md.},
      publisher    = {APS},
      reportid     = {FZJ-2022-01812},
      pages        = {011032},
      year         = {2022},
      abstract     = {Quantum error correction requires the detection of errors
                      via reliable measurements of multiqubit correlation
                      operators. As these operations are inherently faulty,
                      fault-tolerant schemes for realizing quantum error
                      correction are required. Recently, a paradigm requiring only
                      minimal resource overhead in the form of “flag” qubits
                      to detect and correct errors has been proposed. We
                      experimentally demonstrate a fault-tolerant weight-4
                      parity-check measurement scheme, where one additional flag
                      qubit serves to detect errors, which would otherwise
                      proliferate into uncorrectable weight-2 errors onto the
                      qubit register. We achieve a parity measurement fidelity of
                      $92.3(2)\%,$ which increases to $93.2(2)\%$ upon
                      conditioning to the flag readout result, which shows that
                      the measurement scheme intercepts intrinsic errors occurring
                      throughout the sequence. We show that the protocol is
                      capable of reliably intercepting faults by deliberately
                      injecting bit- and phase-flip errors. For holistic
                      benchmarking of the parity measurement scheme, we use an
                      entanglement witnessing scheme requiring a minimal number of
                      measurements to verify genuine six-qubit multipartite
                      entanglement. The demonstrated fault-tolerant parity
                      measurement scheme constitutes the key building block in a
                      broad class of resource-efficient flag-based quantum error
                      correction protocols including topological color codes. Our
                      hardware platform is based on atomic ions stored in a
                      microchip ion trap. The qubit register is dynamically
                      reconfigured via shuttling operations enabling effective
                      full connectivity without operational cross talk, thereby
                      providing key prerequisites underlying fault-tolerant
                      circuit design. These architectural features in combination
                      with the demonstrated approach to flag-based fault-tolerant
                      quantum error correction open up a route toward scalable
                      fault-tolerant quantum computing.},
      cin          = {PGI-2},
      ddc          = {530},
      cid          = {I:(DE-Juel1)PGI-2-20110106},
      pnm          = {5224 - Quantum Networking (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5224},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000761412600001},
      doi          = {10.1103/PhysRevX.12.011032},
      url          = {https://juser.fz-juelich.de/record/907016},
}