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@ARTICLE{Ntinas:907570,
      author       = {Ntinas, Vasileios and Ascoli, Alon and Messaris, Ioannis
                      and Wang, Yongmin and Rana, Vikas and Menzel, Stephan and
                      Tetzlaff, Ronald},
      title        = {{T}oward {S}implified {P}hysics-{B}ased {M}emristor
                      {M}odeling of {V}alence {C}hange {M}echanism {D}evices},
      journal      = {IEEE transactions on circuits and systems / 2},
      volume       = {69},
      number       = {5},
      issn         = {1057-7130},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {FZJ-2022-02087},
      pages        = {2473 - 2477},
      year         = {2022},
      abstract     = {Memristors are promising nanoelectronic devices for the
                      implementation of future AI-driven sensor-processor
                      electronic systems, which are essential for the ongoing
                      digitalization of our world. Accurate and computationally
                      cost-effective models for the manufactured memristors are
                      essential for the design of such systems, especially for the
                      simulation of large circuits. In this brief we address the
                      simplification of the JART memristor model, a generic
                      physics-based model of Valence Change Mechanism (VCM)
                      memristors which accurately describes the dynamic behavior
                      of fabricated memristor devices. Furthermore, the proposed
                      model and simplification methodology have the potential to
                      capture the dynamics of a wide range of memristor devices.
                      Importantly, the implicit description of the current through
                      the memristor is replaced by an explicit mathematical
                      relationship. The proper reproduction of memristor dynamics,
                      verified by applying the system-theoretic Dynamic Route Map
                      (DRM) graphical analysis tool, applicable to first-order
                      systems, can be observed through the proposed simplified
                      model and enables the time-efficient simulation of large
                      arrays of VCM devices.},
      cin          = {PGI-7 / JARA-FIT / PGI-10},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-7-20110106 / $I:(DE-82)080009_20140620$ /
                      I:(DE-Juel1)PGI-10-20170113},
      pnm          = {5233 - Memristive Materials and Devices (POF4-523) /
                      BMBF-16ME0398K - Verbundprojekt: Neuro-inspirierte
                      Technologien der künstlichen Intelligenz für die
                      Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) /
                      BMBF-16ME0399 - Verbundprojekt: Neuro-inspirierte
                      Technologien der künstlichen Intelligenz für die
                      Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0399) / SFB
                      917 B01 - Schnelle transiente, elektrische Analyse von
                      resistiven Schaltphänomenen (B01) (202259360) / ACA -
                      Advanced Computing Architectures (SO-092)},
      pid          = {G:(DE-HGF)POF4-5233 / G:(DE-82)BMBF-16ME0398K /
                      G:(DE-82)BMBF-16ME0399 / G:(GEPRIS)202259360 /
                      G:(DE-HGF)SO-092},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000790814000021},
      doi          = {10.1109/TCSII.2022.3160304},
      url          = {https://juser.fz-juelich.de/record/907570},
}