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000908364 1001_ $$0P:(DE-Juel1)188159$$aBengel, Christopher$$b0$$eCorresponding author$$ufzj
000908364 245__ $$aReliability aspects of binary vector-matrix-multiplications using ReRAM devices
000908364 260__ $$aBristol$$bIOP Publishing Ltd.$$c2022
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000908364 520__ $$aComputation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm's law and Kirchhoff's law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.
000908364 536__ $$0G:(DE-HGF)POF4-5233$$a5233 - Memristive Materials and Devices (POF4-523)$$cPOF4-523$$fPOF IV$$x0
000908364 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF-16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
000908364 536__ $$0G:(DE-82)BMBF-16ME0399$$aBMBF-16ME0399 - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0399)$$cBMBF-16ME0399$$x2
000908364 536__ $$0G:(EU-Grant)780215$$aMNEMOSENE - Computation-in-memory architecture based on resistive devices (780215)$$c780215$$fH2020-ICT-2017-1$$x3
000908364 588__ $$aDataset connected to CrossRef, Journals: juser.fz-juelich.de
000908364 7001_ $$00000-0003-0815-3047$$aMohr, Johannes$$b1
000908364 7001_ $$0P:(DE-Juel1)187229$$aWiefels, Stefan$$b2
000908364 7001_ $$00000-0002-2729-7057$$aSingh, Abhairaj$$b3
000908364 7001_ $$00000-0001-5909-4927$$aGebregiorgis, Anteneh$$b4
000908364 7001_ $$00000-0002-1590-0365$$aBishnoi, Rajendra$$b5
000908364 7001_ $$00000-0002-8961-0387$$aHamdioui, Said$$b6
000908364 7001_ $$0P:(DE-Juel1)131022$$aWaser, Rainer$$b7
000908364 7001_ $$0P:(DE-HGF)0$$aWouters, Dirk$$b8
000908364 7001_ $$0P:(DE-Juel1)158062$$aMenzel, Stephan$$b9
000908364 773__ $$0PERI:(DE-600)3099608-9$$a10.1088/2634-4386/ac6d04$$gVol. 2, no. 3, p. 034001 -$$n3$$p034001 -$$tNeuromorphic computing and engineering$$v2$$x2634-4386$$y2022
000908364 8564_ $$uhttps://juser.fz-juelich.de/record/908364/files/Bengel_2022_Neuromorph._Comput._Eng._2_034001.pdf$$yOpenAccess
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000908364 9141_ $$y2022
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