%0 Conference Paper
%A Junk, Yannik
%A Frauenrath, Marvin
%A Han, Yi
%A Concepción Díaz, Omar
%A Bae, Jin Hee
%A Hartmann, Jean-Michel
%A Grützmacher, Detlev
%A Buca, Dan Mihai
%A Zhao, Qing-Tai
%T GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
%M FZJ-2022-03604
%D 2022
%X Vertical GeSn gate-all-around (GAA) nanowire nMOSFETs fabricated using a top-down approach are presented. The devices are benchmarked with similar Ge and Ge/GeSn/Ge heterostructure devices to underline the great potential of GeSn for future nMOS devices. Device measurements are performed in the temperature range from 12 K to room temperature (RT, 300 K). At RT the all-GeSn n-MOSFETs show a subthreshold swing (SS) of ~120 mV/dec that decreases at cryogenic temperatures to a very steep 20mV/dec. The abrupt transition from subthreshold to on-state shows the suitability of GeSn alloys for cryogenic CMOS applications.
%B IEEE 52nd European Solid State Device Research Conference
%C 19 Sep 2022 - 22 Sep 2022, Milan (Italy)
Y2 19 Sep 2022 - 22 Sep 2022
M2 Milan, Italy
%F PUB:(DE-HGF)6
%9 Conference Presentation
%U https://juser.fz-juelich.de/record/910085