%0 Conference Paper
%A Junk, Yannik
%A Liu, Mingshan
%A Frauenrath, Marvin
%A Hartmann, Jean-Michel
%A Grützmacher, Detlev
%A Buca, Dan Mihai
%A Zhao, Qing-Tai
%T Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs
%M FZJ-2022-03605
%D 2022
%X A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an Ion/Ioff-ratio of 2.1×10^6 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.
%B 241st ECS Meeting
%C 29 May 2022 - 2 Jun 2022, Vancouver (Canada)
Y2 29 May 2022 - 2 Jun 2022
M2 Vancouver, Canada
%F PUB:(DE-HGF)6
%9 Conference Presentation
%U https://juser.fz-juelich.de/record/910086