TY  - CONF
AU  - Junk, Yannik
AU  - Liu, Mingshan
AU  - Frauenrath, Marvin
AU  - Hartmann, Jean-Michel
AU  - Grützmacher, Detlev
AU  - Buca, Dan Mihai
AU  - Zhao, Qing-Tai
TI  - Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs
M1  - FZJ-2022-03605
PY  - 2022
AB  - A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an Ion/Ioff-ratio of 2.1×10^6 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.
T2  - 241st ECS Meeting
CY  - 29 May 2022 - 2 Jun 2022, Vancouver (Canada)
Y2  - 29 May 2022 - 2 Jun 2022
M2  - Vancouver, Canada
LB  - PUB:(DE-HGF)6
UR  - https://juser.fz-juelich.de/record/910086
ER  -