Conference Presentation (Panel discussion)

FZJ-2022-03605

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

Junk, Y. (Corresponding author)FZJ* ; Liu, M.FZJ* ; Frauenrath, M. ; Hartmann, J.-M. ; Grützmacher, D.FZJ* ; Buca, D. M.FZJ* ; Zhao, Q.-T.FZJ*

2022

Abstract: A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an Ion/Ioff-ratio of 2.1×10^6 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)

Research Program(s):

1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)

Appears in the scientific report 2022

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