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000910087 005__ 20221027130516.0
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000910087 1001_ $$0P:(DE-Juel1)185010$$aJunk, Yannik$$b0$$eCorresponding author$$ufzj
000910087 1112_ $$aIEEE 52nd European Solid State Device Research Conference$$cMilan$$d2022-09-19 - 2022-09-22$$gESSDERC$$wItaly
000910087 245__ $$aGeSn Vertical Gate-all-around Nanowire n-type MOSFETs
000910087 260__ $$c2022
000910087 300__ $$a364-367
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000910087 520__ $$aVertical GeSn gate-all-around (GAA) nanowire nMOSFETs fabricated using a top-down approach are presented. The devices are benchmarked with similar Ge and Ge/GeSn/Ge heterostructure devices to underline the great potential of GeSn for future nMOS devices. Device measurements are performed in the temperature range from 12 K to room temperature (RT, 300 K). At RT the all-GeSn n-MOSFETs show a subthreshold swing (SS) of ~120 mV/dec that decreases at cryogenic temperatures to a very steep 20mV/dec. The abrupt transition from subthreshold to on-state shows the suitability of GeSn alloys for cryogenic CMOS applications.
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000910087 7001_ $$0P:(DE-HGF)0$$aFrauenrath, Marvin$$b1
000910087 7001_ $$0P:(DE-Juel1)176845$$aHan, Yi$$b2$$ufzj
000910087 7001_ $$0P:(DE-Juel1)188576$$aConcepción Díaz, Omar$$b3$$ufzj
000910087 7001_ $$0P:(DE-Juel1)177006$$aBae, Jin Hee$$b4$$ufzj
000910087 7001_ $$0P:(DE-HGF)0$$aHartmann, Jean-Michel$$b5
000910087 7001_ $$0P:(DE-Juel1)125588$$aGrützmacher, Detlev$$b6$$ufzj
000910087 7001_ $$0P:(DE-Juel1)125569$$aBuca, Dan Mihai$$b7$$ufzj
000910087 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b8$$ufzj
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000910087 9141_ $$y2022
000910087 9201_ $$0I:(DE-Juel1)PGI-9-20110106$$kPGI-9$$lHalbleiter-Nanoelektronik$$x0
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