TY  - CONF
AU  - Junk, Yannik
AU  - Frauenrath, Marvin
AU  - Han, Yi
AU  - Concepción Díaz, Omar
AU  - Bae, Jin Hee
AU  - Hartmann, Jean-Michel
AU  - Grützmacher, Detlev
AU  - Buca, Dan Mihai
AU  - Zhao, Qing-Tai
TI  - GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
M1  - FZJ-2022-03606
SP  - 364-367
PY  - 2022
AB  - Vertical GeSn gate-all-around (GAA) nanowire nMOSFETs fabricated using a top-down approach are presented. The devices are benchmarked with similar Ge and Ge/GeSn/Ge heterostructure devices to underline the great potential of GeSn for future nMOS devices. Device measurements are performed in the temperature range from 12 K to room temperature (RT, 300 K). At RT the all-GeSn n-MOSFETs show a subthreshold swing (SS) of ~120 mV/dec that decreases at cryogenic temperatures to a very steep 20mV/dec. The abrupt transition from subthreshold to on-state shows the suitability of GeSn alloys for cryogenic CMOS applications.
T2  - IEEE 52nd European Solid State Device Research Conference
CY  - 19 Sep 2022 - 22 Sep 2022, Milan (Italy)
Y2  - 19 Sep 2022 - 22 Sep 2022
M2  - Milan, Italy
LB  - PUB:(DE-HGF)8
UR  - https://juser.fz-juelich.de/record/910087
ER  -