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@INPROCEEDINGS{Focke:912084,
      author       = {Focke, Niels and Struck, Tom and Visser, Lino and Tu,
                      Jhih-Sian and Beer, Max and Schreiber, Lars and Bluhm,
                      Hendrik},
      title        = {{C}oncept of mass-characterization for spin qubit devices
                      on {S}i/{S}i{G}e},
      school       = {RWTH Aachen},
      reportid     = {FZJ-2022-05311},
      year         = {2022},
      abstract     = {With the advancement to more complex spin qubit devices and
                      the employment of industrial CMOS technology for large scale
                      fabrication, fast characterization of the fabricated devices
                      becomes necessary. Furthermore, hysteresis effects have been
                      observed in gate induced transport currents through the
                      quantum well of a Si/SiGe heterostructure [1], which make
                      measurements of SiGe QDs difficult.Here, we present a
                      concept to utilize DC measurements at 4 K for an automated
                      inital characterization of devices used for shuttling of a
                      single electron in a Si/SiGe quantum-channel [2]. This
                      concept improves the throughput of the inital quality
                      control, which identifies devices with functional gates and
                      a stable contact to the quantum well, by utilizing an
                      automated measurement software. Our software performs gate
                      functionality tests and trys to establish an SET without the
                      need of manual input. Additionally, we focus on minimizing
                      charge trapping during the measurement of devices, which is
                      thought to be the cause of the hysteresis observed in the
                      transport current. By employing a cautious approach with as
                      low as possible voltages we find that $70\%$ of measured
                      SETs do not exhibit signatures of charge trapping. This
                      approach also ensures that the maximum of data is collected
                      from each device. Therfore, the fabrication yield of
                      indivdual parts of the device can be determined and the time
                      between device interations is reduced. Furthermore, this
                      concept enables us to use the aggregated data to compare and
                      evaluate different Si/SiGe heterostructures on which the
                      devices are fabricated.[1] A. Wild et al., Appl. Phys. Lett.
                      100, 143110 (2012).[2] I. Seilder et al., arXiv:2108.00879
                      (2021).},
      month         = {Sep},
      date          = {2022-09-05},
      organization  = {Spin Qubit 5, Pontresina
                       (Switzerland), 5 Sep 2022 - 9 Sep 2022},
      subtyp        = {After Call},
      cin          = {PGI-11},
      cid          = {I:(DE-Juel1)PGI-11-20170113},
      pnm          = {5221 - Advanced Solid-State Qubits and Qubit Systems
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5221},
      typ          = {PUB:(DE-HGF)24},
      url          = {https://juser.fz-juelich.de/record/912084},
}