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@INPROCEEDINGS{Trensch:912363,
      author       = {Trensch, Guido and Morrison, Abigail},
      title        = {{A} {S}ystem-on-{C}hip {B}ased {H}ybrid {N}euromorphic
                      {C}ompute ({HNC}) {N}ode {A}rchitecture for {R}eproducible
                      {H}yper-{R}eal-{T}ime {S}imulations of {S}piking {N}eural
                      {N}etworks},
      reportid     = {FZJ-2022-05554},
      year         = {2022},
      abstract     = {Despite the great strides neuroscience has made in recent
                      decades, the underlying principles of brain function remain
                      largely unknown. Advancing the field strongly depends on the
                      ability to study large-scale neural networks and perform
                      complex simulations. In this context, simulations in
                      hyper-real-time are of high interest, but even the fastest
                      supercomputer available today is not able to meet the
                      challenge of accurate and reproducible simulation with
                      hyper-real acceleration. The development of novel
                      neuromorphic computer architectures holds out promise.
                      Advances in System-on-Chip (SoC) device technology and tools
                      are now providing interesting new design possibilities for
                      application-specific implementations. We propose a novel
                      hybrid software-hardware architecture approach for a
                      neuromorphic compute node intended to work in a multi-node
                      cluster configuration. The node design builds on the Xilinx
                      Zynq-7000 SoC device architecture that combines a powerful
                      programmable logic gate array (FPGA) and a dual-core ARM
                      Cortex-A9 processor extension on a single chip. Although
                      high acceleration can be achieved at low workloads, the
                      development also reveals current technological limitations
                      that also apply to CPU implementations of neural network
                      simulation tools.},
      month         = {Sep},
      date          = {2022-09-19},
      organization  = {ACA farewell meeting, Jülich
                       (Germany), 19 Sep 2022 - 20 Sep 2022},
      subtyp        = {Other},
      cin          = {JSC / IAS-6 / INM-6},
      cid          = {I:(DE-Juel1)JSC-20090406 / I:(DE-Juel1)IAS-6-20130828 /
                      I:(DE-Juel1)INM-6-20090406},
      pnm          = {5111 - Domain-Specific Simulation $\&$ Data Life Cycle Labs
                      (SDLs) and Research Groups (POF4-511) / 5234 - Emerging NC
                      Architectures (POF4-523) / ACA - Advanced Computing
                      Architectures (SO-092) / SLNS - SimLab Neuroscience
                      (Helmholtz-SLNS)},
      pid          = {G:(DE-HGF)POF4-5111 / G:(DE-HGF)POF4-5234 /
                      G:(DE-HGF)SO-092 / G:(DE-Juel1)Helmholtz-SLNS},
      typ          = {PUB:(DE-HGF)24},
      url          = {https://juser.fz-juelich.de/record/912363},
}