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| Hauptseite > Publikationsdatenbank > A System-on-Chip Based Hybrid Neuromorphic Compute (HNC) Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks > print |
| Hauptseite > Publikationsdatenbank > A System-on-Chip Based Hybrid Neuromorphic Compute (HNC) Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks > print |
| 001 | 912363 | ||
| 005 | 20240313103134.0 | ||
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| 037 | _ | _ | |a FZJ-2022-05554 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Trensch, Guido |0 P:(DE-Juel1)168379 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a ACA farewell meeting |c Jülich |d 2022-09-19 - 2022-09-20 |w Germany |
| 245 | _ | _ | |a A System-on-Chip Based Hybrid Neuromorphic Compute (HNC) Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks |
| 260 | _ | _ | |c 2022 |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
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| 336 | 7 | _ | |a Poster |b poster |m poster |0 PUB:(DE-HGF)24 |s 1670331405_10042 |2 PUB:(DE-HGF) |x Other |
| 520 | _ | _ | |a Despite the great strides neuroscience has made in recent decades, the underlying principles of brain function remain largely unknown. Advancing the field strongly depends on the ability to study large-scale neural networks and perform complex simulations. In this context, simulations in hyper-real-time are of high interest, but even the fastest supercomputer available today is not able to meet the challenge of accurate and reproducible simulation with hyper-real acceleration. The development of novel neuromorphic computer architectures holds out promise. Advances in System-on-Chip (SoC) device technology and tools are now providing interesting new design possibilities for application-specific implementations. We propose a novel hybrid software-hardware architecture approach for a neuromorphic compute node intended to work in a multi-node cluster configuration. The node design builds on the Xilinx Zynq-7000 SoC device architecture that combines a powerful programmable logic gate array (FPGA) and a dual-core ARM Cortex-A9 processor extension on a single chip. Although high acceleration can be achieved at low workloads, the development also reveals current technological limitations that also apply to CPU implementations of neural network simulation tools. |
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| 700 | 1 | _ | |a Morrison, Abigail |0 P:(DE-Juel1)151166 |b 1 |u fzj |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/912363/files/Poster_SoC_based_NC_node_architecture.pdf |y OpenAccess |
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