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@INPROCEEDINGS{Otten:916924,
      author       = {Otten, R. and Schreckenberg, Lea and Vliex, P. and
                      Ritzmann, J. and Ludwig, A. and Wieck, A. D. and Bluhm, H.},
      title        = {{Q}ubit {B}ias using a {CMOS} {DAC} at m{K} {T}emperatures},
      publisher    = {IEEE},
      reportid     = {FZJ-2023-00192},
      pages        = {1-4},
      year         = {2022},
      abstract     = {Scaling up a quantum processor to tackle real-world
                      problems requires qubit numbers in the millions. Scalable
                      semiconductor-based architectures have been proposed, many
                      of them relying on integrated control instead of
                      room-temperature electronics. However, it has not yet been
                      shown that this can be achieved. For developing a
                      high-density, low-cost wiring solution, it is highly
                      advantageous for the electronics to be placed at the same
                      temperature as the qubit chip. Therefore, tight integration
                      of the qubit chip with ultra low power complemen-tary
                      metal-oxide-semiconductor (CMOS) electronics presents a
                      promising route. We demonstrate DC biasing qubit electrodes
                      using a custom-designed 65nm CMOS capacitive
                      digital-to-analog converter (DAC) operating on the mixing
                      chamber of a dilution refrigerator below 45 mK. Our chip
                      features a complete proof of principle solution including
                      interface, DAC memory and logic, the capacitive DAC, and
                      sample-and-hold structures to provide voltages for multiple
                      qubit gates. The bias- DAC is combined with the qubit using
                      a silicon interposer chip, enabling flexible routing and
                      tight integration. Voltage stability, noise performance, and
                      temperature are benchmarked using the qubit chip. Our
                      results indicate that qubit bias at cryogenic temperatures
                      with a power consumption of 4 n W /ch is feasible with this
                      approach. They validate the potential of very low power
                      qubit biasing using highly integrated circuits whose
                      connectivity requirements do not increase with the number of
                      qubits.},
      month         = {Oct},
      date          = {2022-10-24},
      organization  = {2022 29th IEEE International
                       Conference on Electronics, Circuits and
                       Systems (ICECS), Glasgow (United
                       Kingdom), 24 Oct 2022 - 26 Oct 2022},
      cin          = {PGI-11 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-11-20170113 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5221 - Advanced Solid-State Qubits and Qubit Systems
                      (POF4-522) / BMBF-13N16149 - QSolid (BMBF-13N16149)},
      pid          = {G:(DE-HGF)POF4-5221 / G:(DE-Juel1)BMBF-13N16149},
      typ          = {PUB:(DE-HGF)8},
      url          = {https://juser.fz-juelich.de/record/916924},
}