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| Hauptseite > Publikationsdatenbank > A Low Latency Parallel Bus Interface for High-Speed multi-FPGA RT-Simulations |
| Hauptseite > Publikationsdatenbank > A Low Latency Parallel Bus Interface for High-Speed multi-FPGA RT-Simulations |
| Contribution to a conference proceedings/Contribution to a book | FZJ-2023-01343 |
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2021
IEEE
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Please use a persistent id in citations: doi:10.1109/ESTS49166.2021.9512344
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