TY  - CONF
AU  - Nassyr, Stepan
AU  - Haghighi Mood, Kaveh
AU  - Herten, Andreas
TI  - Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV
M1  - FZJ-2023-03437
PY  - 2023
AB  - In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the A64FX processor. We use the same approach to generate RISC-V RVV 0.7.1 kernels for the Allwinner D1, a commercially available non-HPC RISC-V processor with support for a draft version of the RVV extension, as well as the FPGA SDV (RVV 0.7.1) of the in-development EUPILOT VEC accelerator and evaluate the performance
T2  - RISC-V Summit Europe 2023
CY  - 5 Jun 2023 - 9 Jun 2023, Barcelona (Spain)
Y2  - 5 Jun 2023 - 9 Jun 2023
M2  - Barcelona, Spain
LB  - PUB:(DE-HGF)24
DO  - DOI:10.34734/FZJ-2023-03437
UR  - https://juser.fz-juelich.de/record/1014748
ER  -