Poster (Other)

FZJ-2023-03437

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV

Nassyr, S. (Corresponding author)FZJ* ; Haghighi Mood, K.FZJ* ; Herten, A.FZJ*

2023

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Please use a persistent id in citations: doi:10.34734/FZJ-2023-03437

Abstract: In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the A64FX processor. We use the same approach to generate RISC-V RVV 0.7.1 kernels for the Allwinner D1, a commercially available non-HPC RISC-V processor with support for a draft version of the RVV extension, as well as the FPGA SDV (RVV 0.7.1) of the in-development EUPILOT VEC accelerator and evaluate the performance

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Contributing Institute(s):

1. Jülich Supercomputing Center (JSC)

Research Program(s):

1. 5122 - Future Computing & Big Data Systems (POF4-512) (POF4-512)
2. PhD no Grant - Doktorand ohne besondere Förderung (PHD-NO-GRANT-20170405) (PHD-NO-GRANT-20170405)
3. The European PILOT - Pilot using Independent Local & Open Technologies (101034126) (101034126)
4. ATML-X-DEV - ATML Accelerating Devices (ATML-X-DEV) (ATML-X-DEV)

Appears in the scientific report 2023

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Database coverage:

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