001     1014748
005     20250822121410.0
024 7 _ |a 10.34734/FZJ-2023-03437
|2 datacite_doi
037 _ _ |a FZJ-2023-03437
041 _ _ |a English
100 1 _ |a Nassyr, Stepan
|0 P:(DE-Juel1)172888
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|e Corresponding author
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111 2 _ |a RISC-V Summit Europe 2023
|c Barcelona
|d 2023-06-05 - 2023-06-09
|w Spain
245 _ _ |a Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV
260 _ _ |c 2023
336 7 _ |a Conference Paper
|0 33
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336 7 _ |a INPROCEEDINGS
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336 7 _ |a conferenceObject
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336 7 _ |a CONFERENCE_POSTER
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336 7 _ |a Output Types/Conference Poster
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336 7 _ |a Poster
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520 _ _ |a In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the A64FX processor. We use the same approach to generate RISC-V RVV 0.7.1 kernels for the Allwinner D1, a commercially available non-HPC RISC-V processor with support for a draft version of the RVV extension, as well as the FPGA SDV (RVV 0.7.1) of the in-development EUPILOT VEC accelerator and evaluate the performance
536 _ _ |a 5122 - Future Computing & Big Data Systems (POF4-512)
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536 _ _ |a PhD no Grant - Doktorand ohne besondere Förderung (PHD-NO-GRANT-20170405)
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536 _ _ |a The European PILOT - Pilot using Independent Local & Open Technologies (101034126)
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536 _ _ |a ATML-X-DEV - ATML Accelerating Devices (ATML-X-DEV)
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700 1 _ |a Haghighi Mood, Kaveh
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700 1 _ |a Herten, Andreas
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856 4 _ |u https://riscv-europe.org/media/proceedings/posters/2023-06-07-Stepan-NASSYR-poster.pdf
856 4 _ |u https://juser.fz-juelich.de/record/1014748/files/Extended%20Abstract.pdf
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856 4 _ |u https://juser.fz-juelich.de/record/1014748/files/Poster.pdf
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909 C O |o oai:juser.fz-juelich.de:1014748
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910 1 _ |a Forschungszentrum Jülich
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914 1 _ |y 2023
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