Home > Publications database > Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV > print |
001 | 1014748 | ||
005 | 20250822121410.0 | ||
024 | 7 | _ | |a 10.34734/FZJ-2023-03437 |2 datacite_doi |
037 | _ | _ | |a FZJ-2023-03437 |
041 | _ | _ | |a English |
100 | 1 | _ | |a Nassyr, Stepan |0 P:(DE-Juel1)172888 |b 0 |e Corresponding author |u fzj |
111 | 2 | _ | |a RISC-V Summit Europe 2023 |c Barcelona |d 2023-06-05 - 2023-06-09 |w Spain |
245 | _ | _ | |a Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV |
260 | _ | _ | |c 2023 |
336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
336 | 7 | _ | |a conferenceObject |2 DRIVER |
336 | 7 | _ | |a CONFERENCE_POSTER |2 ORCID |
336 | 7 | _ | |a Output Types/Conference Poster |2 DataCite |
336 | 7 | _ | |a Poster |b poster |m poster |0 PUB:(DE-HGF)24 |s 1701334222_23445 |2 PUB:(DE-HGF) |x Other |
520 | _ | _ | |a In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the A64FX processor. We use the same approach to generate RISC-V RVV 0.7.1 kernels for the Allwinner D1, a commercially available non-HPC RISC-V processor with support for a draft version of the RVV extension, as well as the FPGA SDV (RVV 0.7.1) of the in-development EUPILOT VEC accelerator and evaluate the performance |
536 | _ | _ | |a 5122 - Future Computing & Big Data Systems (POF4-512) |0 G:(DE-HGF)POF4-5122 |c POF4-512 |f POF IV |x 0 |
536 | _ | _ | |a PhD no Grant - Doktorand ohne besondere Förderung (PHD-NO-GRANT-20170405) |0 G:(DE-Juel1)PHD-NO-GRANT-20170405 |c PHD-NO-GRANT-20170405 |x 1 |
536 | _ | _ | |a The European PILOT - Pilot using Independent Local & Open Technologies (101034126) |0 G:(EU-Grant)101034126 |c 101034126 |f H2020-JTI-EuroHPC-2020-1 |x 2 |
536 | _ | _ | |a ATML-X-DEV - ATML Accelerating Devices (ATML-X-DEV) |0 G:(DE-Juel-1)ATML-X-DEV |c ATML-X-DEV |x 3 |
700 | 1 | _ | |a Haghighi Mood, Kaveh |0 P:(DE-Juel1)176293 |b 1 |u fzj |
700 | 1 | _ | |a Herten, Andreas |0 P:(DE-Juel1)145478 |b 2 |u fzj |
856 | 4 | _ | |u https://riscv-europe.org/media/proceedings/posters/2023-06-07-Stepan-NASSYR-poster.pdf |
856 | 4 | _ | |u https://juser.fz-juelich.de/record/1014748/files/Extended%20Abstract.pdf |y OpenAccess |
856 | 4 | _ | |u https://juser.fz-juelich.de/record/1014748/files/Poster.pdf |y OpenAccess |
909 | C | O | |o oai:juser.fz-juelich.de:1014748 |p openaire |p open_access |p VDB |p driver |p ec_fundedresources |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)172888 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)176293 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)145478 |
913 | 1 | _ | |a DE-HGF |b Key Technologies |l Engineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action |1 G:(DE-HGF)POF4-510 |0 G:(DE-HGF)POF4-512 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Supercomputing & Big Data Infrastructures |9 G:(DE-HGF)POF4-5122 |x 0 |
914 | 1 | _ | |y 2023 |
915 | _ | _ | |a OpenAccess |0 StatID:(DE-HGF)0510 |2 StatID |
920 | _ | _ | |l yes |
920 | 1 | _ | |0 I:(DE-Juel1)JSC-20090406 |k JSC |l Jülich Supercomputing Center |x 0 |
980 | _ | _ | |a poster |
980 | _ | _ | |a VDB |
980 | _ | _ | |a UNRESTRICTED |
980 | _ | _ | |a I:(DE-Juel1)JSC-20090406 |
980 | 1 | _ | |a FullTexts |
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