%0 Conference Paper
%A Portero, Antonio
%A Falquez, Carlos
%A Ho, Nam
%A Petrakis, Polydoros
%A Nassyr, Stepan
%A Marazakis, Manolis
%A Dolbeau, Romain
%A Nocua Cifuentes, Jorge A.
%A Beltran, Luis
%A Pleiter, Dirk
%A Suarez, Estela
%T COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores
%V 13949
%C Cham
%I Springer Nature Switzerland
%M FZJ-2023-05391
%@ 978-3-031-42784-8
%B Lecture Notes in Computer Science
%P 105-119
%D 2023
%Z Grant Name: EPI-SGA2
%< Architecture of Computing Systems - 36th International Conference
%X This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.
%B Architecture of Computing Systems - 36th International Conference
%C 13 Jun 2023 - 15 Jun 2023, Athens (Greece)
Y2 13 Jun 2023 - 15 Jun 2023
M2 Athens, Greece
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%U <Go to ISI:>//WOS:001293532100008
%R 10.1007/978-3-031-42785-5_8
%U https://juser.fz-juelich.de/record/1019434