Contribution to a conference proceedings/Contribution to a book

FZJ-2023-05391

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores

Portero, A. (Corresponding author)FZJ* ; Falquez, C.FZJ* ; Ho, N.FZJ* ; Petrakis, P. ; Nassyr, S.FZJ* ; Marazakis, M. ; Dolbeau, R. ; Nocua Cifuentes, J. A. ; Beltran, L. ; Pleiter, D. ; Suarez, E.FZJ*

2023
Springer Nature Switzerland Cham
ISBN: 978-3-031-42784-8, 978-3-031-42785-5 (electronic)

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Please use a persistent id in citations: doi:10.1007/978-3-031-42785-5_8  doi:10.34734/FZJ-2023-05391

Abstract: This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.

Note: Grant Name: EPI-SGA2

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Contributing Institute(s):

1. Jülich Supercomputing Center (JSC)
2. Institute for Advanced Simulation (IAS)

Research Program(s):

1. 5122 - Future Computing & Big Data Systems (POF4-512) (POF4-512)
2. EPI SGA1 - SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI) (826647) (826647)

Appears in the scientific report 2023

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Database coverage:
; Nationallizenz ; SCOPUS

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