001019434 001__ 1019434
001019434 005__ 20241023094527.0
001019434 0247_ $$2doi$$a10.1007/978-3-031-42785-5_8
001019434 0247_ $$2ISSN$$a0302-9743
001019434 0247_ $$2ISSN$$a1611-3349
001019434 0247_ $$2datacite_doi$$a10.34734/FZJ-2023-05391
001019434 0247_ $$2WOS$$aWOS:001293532100008
001019434 020__ $$a978-3-031-42784-8
001019434 020__ $$a978-3-031-42785-5 (electronic)
001019434 037__ $$aFZJ-2023-05391
001019434 1001_ $$0P:(DE-Juel1)177768$$aPortero, Antonio$$b0$$eCorresponding author$$ufzj
001019434 1112_ $$aArchitecture of Computing Systems - 36th International Conference$$cAthens$$d2023-06-13 - 2023-06-15$$gARCS2023$$wGreece
001019434 245__ $$aCOMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores
001019434 260__ $$aCham$$bSpringer Nature Switzerland$$c2023
001019434 29510 $$aArchitecture of Computing Systems - 36th International Conference
001019434 300__ $$a105-119
001019434 3367_ $$2ORCID$$aCONFERENCE_PAPER
001019434 3367_ $$033$$2EndNote$$aConference Paper
001019434 3367_ $$2BibTeX$$aINPROCEEDINGS
001019434 3367_ $$2DRIVER$$aconferenceObject
001019434 3367_ $$2DataCite$$aOutput Types/Conference Paper
001019434 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1703066963_24344
001019434 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book$$mcontb
001019434 4900_ $$aLecture Notes in Computer Science$$v13949
001019434 500__ $$aGrant Name: EPI-SGA2
001019434 520__ $$aThis paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.
001019434 536__ $$0G:(DE-HGF)POF4-5122$$a5122 - Future Computing & Big Data Systems (POF4-512)$$cPOF4-512$$fPOF IV$$x0
001019434 536__ $$0G:(EU-Grant)826647$$aEPI SGA1 - SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI) (826647)$$c826647$$fH2020-SGA-LPMT-2018$$x1
001019434 588__ $$aDataset connected to CrossRef Book Series, Journals: juser.fz-juelich.de
001019434 7001_ $$0P:(DE-Juel1)179531$$aFalquez, Carlos$$b1
001019434 7001_ $$0P:(DE-Juel1)176469$$aHo, Nam$$b2
001019434 7001_ $$0P:(DE-HGF)0$$aPetrakis, Polydoros$$b3
001019434 7001_ $$0P:(DE-Juel1)172888$$aNassyr, Stepan$$b4
001019434 7001_ $$0P:(DE-HGF)0$$aMarazakis, Manolis$$b5
001019434 7001_ $$0P:(DE-HGF)0$$aDolbeau, Romain$$b6
001019434 7001_ $$0P:(DE-HGF)0$$aNocua Cifuentes, Jorge A.$$b7
001019434 7001_ $$0P:(DE-HGF)0$$aBeltran, Luis$$b8
001019434 7001_ $$0P:(DE-Juel1)144441$$aPleiter, Dirk$$b9
001019434 7001_ $$0P:(DE-Juel1)142361$$aSuarez, Estela$$b10
001019434 773__ $$a10.1007/978-3-031-42785-5_8
001019434 8564_ $$uhttps://link.springer.com/chapter/10.1007/978-3-031-42785-5_8
001019434 8564_ $$uhttps://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.pdf$$yOpenAccess
001019434 8564_ $$uhttps://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.gif?subformat=icon$$xicon$$yOpenAccess
001019434 8564_ $$uhttps://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-1440$$xicon-1440$$yOpenAccess
001019434 8564_ $$uhttps://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-180$$xicon-180$$yOpenAccess
001019434 8564_ $$uhttps://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-640$$xicon-640$$yOpenAccess
001019434 909CO $$ooai:juser.fz-juelich.de:1019434$$pdnbdelivery$$pec_fundedresources$$pVDB$$pdriver$$popen_access$$popenaire
001019434 915__ $$0StatID:(DE-HGF)0200$$2StatID$$aDBCoverage$$bSCOPUS$$d2023-09-03
001019434 915__ $$0StatID:(DE-HGF)0510$$2StatID$$aOpenAccess
001019434 915__ $$0StatID:(DE-HGF)0420$$2StatID$$aNationallizenz$$d2023-09-03$$wger
001019434 9141_ $$y2023
001019434 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)177768$$aForschungszentrum Jülich$$b0$$kFZJ
001019434 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)179531$$aForschungszentrum Jülich$$b1$$kFZJ
001019434 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176469$$aForschungszentrum Jülich$$b2$$kFZJ
001019434 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)172888$$aForschungszentrum Jülich$$b4$$kFZJ
001019434 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142361$$aForschungszentrum Jülich$$b10$$kFZJ
001019434 9131_ $$0G:(DE-HGF)POF4-512$$1G:(DE-HGF)POF4-510$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5122$$aDE-HGF$$bKey Technologies$$lEngineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action$$vSupercomputing & Big Data Infrastructures$$x0
001019434 920__ $$lyes
001019434 9201_ $$0I:(DE-Juel1)JSC-20090406$$kJSC$$lJülich Supercomputing Center$$x0
001019434 9201_ $$0I:(DE-Juel1)VDB1106$$kIAS$$lInstitute for Advanced Simulation$$x1
001019434 980__ $$acontrib
001019434 980__ $$aVDB
001019434 980__ $$aUNRESTRICTED
001019434 980__ $$acontb
001019434 980__ $$aI:(DE-Juel1)JSC-20090406
001019434 980__ $$aI:(DE-Juel1)VDB1106
001019434 9801_ $$aFullTexts