TY  - CONF
AU  - Portero, Antonio
AU  - Falquez, Carlos
AU  - Ho, Nam
AU  - Petrakis, Polydoros
AU  - Nassyr, Stepan
AU  - Marazakis, Manolis
AU  - Dolbeau, Romain
AU  - Nocua Cifuentes, Jorge A.
AU  - Beltran, Luis
AU  - Pleiter, Dirk
AU  - Suarez, Estela
TI  - COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores
VL  - 13949
CY  - Cham
PB  - Springer Nature Switzerland
M1  - FZJ-2023-05391
SN  - 978-3-031-42784-8
T2  - Lecture Notes in Computer Science
SP  - 105-119
PY  - 2023
N1  - Grant Name: EPI-SGA2
AB  - This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.
T2  - Architecture of Computing Systems - 36th International Conference
CY  - 13 Jun 2023 - 15 Jun 2023, Athens (Greece)
Y2  - 13 Jun 2023 - 15 Jun 2023
M2  - Athens, Greece
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
UR  - <Go to ISI:>//WOS:001293532100008
DO  - DOI:10.1007/978-3-031-42785-5_8
UR  - https://juser.fz-juelich.de/record/1019434
ER  -