Gast ::
| Hauptseite > Publikationsdatenbank > COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores > print |
| Hauptseite > Publikationsdatenbank > COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores > print |
| 001 | 1019434 | ||
| 005 | 20241023094527.0 | ||
| 020 | _ | _ | |a 978-3-031-42784-8 |
| 020 | _ | _ | |a 978-3-031-42785-5 (electronic) |
| 024 | 7 | _ | |2 doi |a 10.1007/978-3-031-42785-5_8 |
| 024 | 7 | _ | |2 ISSN |a 0302-9743 |
| 024 | 7 | _ | |2 ISSN |a 1611-3349 |
| 024 | 7 | _ | |2 datacite_doi |a 10.34734/FZJ-2023-05391 |
| 024 | 7 | _ | |a WOS:001293532100008 |2 WOS |
| 037 | _ | _ | |a FZJ-2023-05391 |
| 100 | 1 | _ | |0 P:(DE-Juel1)177768 |a Portero, Antonio |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a Architecture of Computing Systems - 36th International Conference |c Athens |d 2023-06-13 - 2023-06-15 |g ARCS2023 |w Greece |
| 245 | _ | _ | |a COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores |
| 260 | _ | _ | |a Cham |b Springer Nature Switzerland |c 2023 |
| 295 | 1 | 0 | |a Architecture of Computing Systems - 36th International Conference |
| 300 | _ | _ | |a 105-119 |
| 336 | 7 | _ | |2 ORCID |a CONFERENCE_PAPER |
| 336 | 7 | _ | |0 33 |2 EndNote |a Conference Paper |
| 336 | 7 | _ | |2 BibTeX |a INPROCEEDINGS |
| 336 | 7 | _ | |2 DRIVER |a conferenceObject |
| 336 | 7 | _ | |2 DataCite |a Output Types/Conference Paper |
| 336 | 7 | _ | |0 PUB:(DE-HGF)8 |2 PUB:(DE-HGF) |a Contribution to a conference proceedings |b contrib |m contrib |s 1703066963_24344 |
| 336 | 7 | _ | |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |a Contribution to a book |m contb |
| 490 | 0 | _ | |a Lecture Notes in Computer Science |v 13949 |
| 500 | _ | _ | |a Grant Name: EPI-SGA2 |
| 520 | _ | _ | |a This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system. |
| 536 | _ | _ | |0 G:(DE-HGF)POF4-5122 |a 5122 - Future Computing & Big Data Systems (POF4-512) |c POF4-512 |f POF IV |x 0 |
| 536 | _ | _ | |0 G:(EU-Grant)826647 |a EPI SGA1 - SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI) (826647) |c 826647 |f H2020-SGA-LPMT-2018 |x 1 |
| 588 | _ | _ | |a Dataset connected to CrossRef Book Series, Journals: juser.fz-juelich.de |
| 700 | 1 | _ | |0 P:(DE-Juel1)179531 |a Falquez, Carlos |b 1 |
| 700 | 1 | _ | |0 P:(DE-Juel1)176469 |a Ho, Nam |b 2 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Petrakis, Polydoros |b 3 |
| 700 | 1 | _ | |0 P:(DE-Juel1)172888 |a Nassyr, Stepan |b 4 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Marazakis, Manolis |b 5 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Dolbeau, Romain |b 6 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Nocua Cifuentes, Jorge A. |b 7 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Beltran, Luis |b 8 |
| 700 | 1 | _ | |0 P:(DE-Juel1)144441 |a Pleiter, Dirk |b 9 |
| 700 | 1 | _ | |0 P:(DE-Juel1)142361 |a Suarez, Estela |b 10 |
| 773 | _ | _ | |a 10.1007/978-3-031-42785-5_8 |
| 856 | 4 | _ | |u https://link.springer.com/chapter/10.1007/978-3-031-42785-5_8 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.pdf |y OpenAccess |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.gif?subformat=icon |x icon |y OpenAccess |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-1440 |x icon-1440 |y OpenAccess |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-180 |x icon-180 |y OpenAccess |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1019434/files/arcs2023-OPIS.jpg?subformat=icon-640 |x icon-640 |y OpenAccess |
| 909 | C | O | |o oai:juser.fz-juelich.de:1019434 |p openaire |p open_access |p driver |p VDB |p ec_fundedresources |p dnbdelivery |
| 910 | 1 | _ | |0 I:(DE-588b)5008462-8 |6 P:(DE-Juel1)177768 |a Forschungszentrum Jülich |b 0 |k FZJ |
| 910 | 1 | _ | |0 I:(DE-588b)5008462-8 |6 P:(DE-Juel1)179531 |a Forschungszentrum Jülich |b 1 |k FZJ |
| 910 | 1 | _ | |0 I:(DE-588b)5008462-8 |6 P:(DE-Juel1)176469 |a Forschungszentrum Jülich |b 2 |k FZJ |
| 910 | 1 | _ | |0 I:(DE-588b)5008462-8 |6 P:(DE-Juel1)172888 |a Forschungszentrum Jülich |b 4 |k FZJ |
| 910 | 1 | _ | |0 I:(DE-588b)5008462-8 |6 P:(DE-Juel1)142361 |a Forschungszentrum Jülich |b 10 |k FZJ |
| 913 | 1 | _ | |0 G:(DE-HGF)POF4-512 |1 G:(DE-HGF)POF4-510 |2 G:(DE-HGF)POF4-500 |3 G:(DE-HGF)POF4 |4 G:(DE-HGF)POF |9 G:(DE-HGF)POF4-5122 |a DE-HGF |b Key Technologies |l Engineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action |v Supercomputing & Big Data Infrastructures |x 0 |
| 914 | 1 | _ | |y 2023 |
| 915 | _ | _ | |0 StatID:(DE-HGF)0200 |2 StatID |a DBCoverage |b SCOPUS |d 2023-09-03 |
| 915 | _ | _ | |0 StatID:(DE-HGF)0510 |2 StatID |a OpenAccess |
| 915 | _ | _ | |0 StatID:(DE-HGF)0420 |2 StatID |a Nationallizenz |d 2023-09-03 |w ger |
| 920 | _ | _ | |l yes |
| 920 | 1 | _ | |0 I:(DE-Juel1)JSC-20090406 |k JSC |l Jülich Supercomputing Center |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)VDB1106 |k IAS |l Institute for Advanced Simulation |x 1 |
| 980 | _ | _ | |a contrib |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a UNRESTRICTED |
| 980 | _ | _ | |a contb |
| 980 | _ | _ | |a I:(DE-Juel1)JSC-20090406 |
| 980 | _ | _ | |a I:(DE-Juel1)VDB1106 |
| 980 | 1 | _ | |a FullTexts |
| Library | Collection | CLSMajor | CLSMinor | Language | Author |
|---|