| Home > Publications database > COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores > print |
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| 024 | 7 | _ | |2 doi |a 10.1007/978-3-031-42785-5_8 |
| 024 | 7 | _ | |2 ISSN |a 0302-9743 |
| 024 | 7 | _ | |2 ISSN |a 1611-3349 |
| 024 | 7 | _ | |2 datacite_doi |a 10.34734/FZJ-2023-05391 |
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| 037 | _ | _ | |a FZJ-2023-05391 |
| 100 | 1 | _ | |0 P:(DE-Juel1)177768 |a Portero, Antonio |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a Architecture of Computing Systems - 36th International Conference |c Athens |d 2023-06-13 - 2023-06-15 |g ARCS2023 |w Greece |
| 245 | _ | _ | |a COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores |
| 260 | _ | _ | |a Cham |b Springer Nature Switzerland |c 2023 |
| 295 | 1 | 0 | |a Architecture of Computing Systems - 36th International Conference |
| 300 | _ | _ | |a 105-119 |
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| 490 | 0 | _ | |a Lecture Notes in Computer Science |v 13949 |
| 500 | _ | _ | |a Grant Name: EPI-SGA2 |
| 520 | _ | _ | |a This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system. |
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| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Petrakis, Polydoros |b 3 |
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| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Dolbeau, Romain |b 6 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Nocua Cifuentes, Jorge A. |b 7 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Beltran, Luis |b 8 |
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| 773 | _ | _ | |a 10.1007/978-3-031-42785-5_8 |
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