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@INPROCEEDINGS{Krystofiak:1020305,
      author       = {Krystofiak, Lukas and Christ, Volker and Kusuma, Sabitha
                      and Grewing, Christian and Zambanini, Andre and van Waasen,
                      Stefan},
      title        = {{A} {S}oftware-{S}calable {A}nalog-{T}o-{D}igital
                      {C}onverter for {P}article {D}etectors in 28{NM} {BULK}
                      {CMOS}},
      reportid     = {FZJ-2024-00047},
      year         = {2023},
      abstract     = {New discoveries in particle physics put an
                      everincreasingdemand on the installed electronics in
                      detector experiments.Currently used process technologies for
                      integratedelectronics, as 65nm and larger, are reaching
                      their limits ofresolution over power consumption and
                      integration factor. Theconsequential progression to a
                      smaller process technology comeswith increased cost and
                      design complexity resulting in a higherimpact on the overall
                      success of a project. The currently discussedway out of this
                      predicament is concentrating cost and effortin fewer, more
                      generic solutions covering a wider range ofapplications. A
                      first prototype of a software-scalable Analog-to-Digital
                      converter manufactured in a 28nm bulk CMOS processtechnology
                      is presented, which is part of a generic frontendsolution
                      concept. It incorporates a low-power mode with 8 bit
                      ofresolution, a maximum sample rate of 480 MSPS, and a
                      powerconsumption of 1.62mW. When higher resolution is
                      needed, ahigh-precision mode can be used with a resolution
                      of 11 bit, amaximum sample rate of 350 MSPS and a power
                      consumptionof 5.6mW. The complete software-scalable
                      Analog-to-Digitalconverter takes 0.029mm2 of chip area.
                      Overall, the first chipis 1mm2 in size. It includes two
                      channels, a high-speed parallelcommunication interface, a
                      clock buffer and memory for 8168Analog-to-Digital converter
                      samples.},
      month         = {Nov},
      date          = {2023-11-04},
      organization  = {2023 IEEE NSS MIC RTSD, Vancouver BC
                       (Canada), 4 Nov 2023 - 11 Nov 2023},
      subtyp        = {After Call},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {622 - Detector Technologies and Systems (POF4-622)},
      pid          = {G:(DE-HGF)POF4-622},
      typ          = {PUB:(DE-HGF)24},
      url          = {https://juser.fz-juelich.de/record/1020305},
}