guest ::
| Home > Publications database > Co-Simulation and Optimization of Semiconductor Spin Qubits with Cryogenic Integrated Electronics |
| Home > Publications database > Co-Simulation and Optimization of Semiconductor Spin Qubits with Cryogenic Integrated Electronics |
| Poster (After Call) | FZJ-2024-01217 |
; ;
2023
Abstract: In order to realize quantum computers that serve a broad range of applications, quantum error correction is necessary to minimize the error rate caused by various disturbances. This requires quantum processors to have a large number of qubits with high operation fidelities.Silicon spin qubits in quantum dots are a promising candidate to meet these requirements, because they provide the advantage of large-scale 3D integration with industrial CMOS processes. However, inherent non-ideal effects of electronics, such as noise, power consumption and crosstalk affect the qubit fidelity. Moreover, requirements for a minimum qubit fidelity are commonly difficult or impossible to translate to accurate, unambiguous requirements for electronics. Consequently, an environment enabling the co-design and co-simulation of the quantum system together with the integrated electronics is indispensable to reach a truly scalable hybrid system. We developed a methodology that uses Python as an interface between the quantum simulator and the circuit simulator. From within Python, many different tool packages specifically for quantum simulation are accessible, while an interface to the Cadence Spectre simulator enables including the effects of integrated electronics. The circuit netlist can be imported unaltered and an explicit understanding of the circuit behavior or the Cadence simulation environment is not necessary. We demonstrate the proposed methodology with a co-optimization loop involving a circuit for the generation of control signals for an electron-shuttling device. This so-called Quantum Bus (QuBus) is an important building block of the SpinBus architecture, which is a recently proposed large-scale quantum processor architecture based on Si/SiGe qubits [1].[1] Künne, M. et al. The spinbus architecture: Scaling spin qubits with electron shuttling. Preprint at https://arxiv.org/abs/2306.16348 (2023).
|
The record appears in these collections: |