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@INPROCEEDINGS{Duipmans:1022080,
author = {Duipmans, Lammert and van Waasen, Stefan and Geck, Lotte},
title = {{C}o-{S}imulation and {O}ptimization of {S}emiconductor
{S}pin {Q}ubits with {C}ryogenic {I}ntegrated {E}lectronics},
reportid = {FZJ-2024-01217},
year = {2023},
abstract = {In order to realize quantum computers that serve a broad
range of applications, quantum error correction is necessary
to minimize the error rate caused by various disturbances.
This requires quantum processors to have a large number of
qubits with high operation fidelities.Silicon spin qubits in
quantum dots are a promising candidate to meet these
requirements, because they provide the advantage of
large-scale 3D integration with industrial CMOS processes.
However, inherent non-ideal effects of electronics, such as
noise, power consumption and crosstalk affect the qubit
fidelity. Moreover, requirements for a minimum qubit
fidelity are commonly difficult or impossible to translate
to accurate, unambiguous requirements for electronics.
Consequently, an environment enabling the co-design and
co-simulation of the quantum system together with the
integrated electronics is indispensable to reach a truly
scalable hybrid system. We developed a methodology that uses
Python as an interface between the quantum simulator and the
circuit simulator. From within Python, many different tool
packages specifically for quantum simulation are accessible,
while an interface to the Cadence Spectre simulator enables
including the effects of integrated electronics. The circuit
netlist can be imported unaltered and an explicit
understanding of the circuit behavior or the Cadence
simulation environment is not necessary. We demonstrate the
proposed methodology with a co-optimization loop involving a
circuit for the generation of control signals for an
electron-shuttling device. This so-called Quantum Bus
(QuBus) is an important building block of the SpinBus
architecture, which is a recently proposed large-scale
quantum processor architecture based on Si/SiGe qubits
[1].[1] Künne, M. et al. The spinbus architecture: Scaling
spin qubits with electron shuttling. Preprint at
https://arxiv.org/abs/2306.16348 (2023).},
month = {Oct},
date = {2023-10-31},
organization = {Silicon Quantum Electronics Workshop
2023, Kyoto (Japan), 31 Oct 2023 - 2
Nov 2023},
subtyp = {After Call},
cin = {ZEA-2},
cid = {I:(DE-Juel1)ZEA-2-20090406},
pnm = {5223 - Quantum-Computer Control Systems and Cryoelectronics
(POF4-522)},
pid = {G:(DE-HGF)POF4-5223},
typ = {PUB:(DE-HGF)24},
url = {https://juser.fz-juelich.de/record/1022080},
}