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| Hauptseite > Publikationsdatenbank > The SpinBus Architecture: Scaling Spin Qubits with Electron Shuttling |
| Hauptseite > Publikationsdatenbank > The SpinBus Architecture: Scaling Spin Qubits with Electron Shuttling |
| Preprint | FZJ-2024-01806 |
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2023
arXiv
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Please use a persistent id in citations: doi:10.48550/ARXIV.2306.16348 doi:10.34734/FZJ-2024-01806
Abstract: Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9 %. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.
Keyword(s): Quantum Physics (quant-ph) ; Mesoscale and Nanoscale Physics (cond-mat.mes-hall) ; FOS: Physical sciences
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