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| Hauptseite > Publikationsdatenbank > 2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28 nm CMOS Technology |
| Hauptseite > Publikationsdatenbank > 2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28 nm CMOS Technology |
| Poster (After Call) | FZJ-2024-05534 |
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2024
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Please use a persistent id in citations: doi:10.34734/FZJ-2024-05534
Abstract: Memristors are promising devices for scalable andlow power, in-memory computing to improve the energy efficiencyof a rising computational demand. The crossbar array architecturewith memristors is used for vector matrix multiplication(VMM) and acts as kernels in neuromorphic computing. Theanalog conductance control in a memristor is achieved byapplying voltage or current through it. A basic 1T1R arrayis suitable to avoid sneak path issues but suffer from wireresistances, which affects the read and write procedures. Aconductance control scheme with a regulated voltage sourcewill improve the architecture and reduce the possible potentialdivider effects. A change in conductance is also possible with theprovision of a regulated current source and measuring the voltageacross the memristors. A regulated 2T1R memristor conductancecontrol architecture is proposed in this work, which avoids thepotential divider effect and virtual ground scenario in a regularcrossbar scheme, as well as conductance control by passing aregulated current through memristors. The sneak path currentis not allowed to pass by the provision of ground potential toboth terminals of memristors.
Keyword(s): Engineering, Industrial Materials and Processing (1st)
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