TY  - JOUR
AU  - Brackmann, Leon
AU  - Ziegler, Tobias
AU  - Wouters, Dirk J.
AU  - Menzel, Stephan
TI  - Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM
JO  - IEEE transactions on circuits and systems / 1
VL  - 72
IS  - 5
SN  - 1549-8328
CY  - New York, NY
PB  - Institute of Electrical and Electronics Engineers
M1  - FZJ-2024-07014
SP  - 2029 - 2038
PY  - 2025
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:001346643000001
DO  - DOI:10.1109/TCSI.2024.3486376
UR  - https://juser.fz-juelich.de/record/1034225
ER  -