TY  - CONF
AU  - Zhao, Wei
AU  - Kuriakose, Neethu
AU  - Kusuma, Sabitha
AU  - Ammari, Abdelaziz
AU  - Ashok, Arun
AU  - Grewing, Christian
AU  - Zambanini, André
AU  - Van Waasen, Stefan
TI  - On-Chip Advanced Control Algorithm for Memristor Operations with Integrated RISC-V Core
CY  - Nancy
PB  - IEEE
M1  - FZJ-2025-01656
SN  - 979-8-3503-7720-0
SP  - 1-4
PY  - 2024
AB  - Advancements in memory technology havepositioned memristors at the forefront of non-volatile memoryapplications, necessitating precise control mechanisms toaccurately program memristor cells to their respective states.This study delves into the utilization of a RISC-V processor andPWM generators to configure registers for analog conductancecontrol of crossbar memristor array architecture for accuratevoltage and current mode operations. The core contribution isthe development of a flexible and efficient control algorithmspecifically designed for RISC-V. A Universal VerificationMethodology Framework (UVMF) testbench is employedto validate control signals, ensuring their accuracy priorto hardware implementation. Results indicate significantenhancements in control efficiency, underlining the potential forintegrating RISC-V with memristor technology.
T2  - 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
CY  - 18 Nov 2024 - 20 Nov 2024, Nancy (France)
Y2  - 18 Nov 2024 - 20 Nov 2024
M2  - Nancy, France
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
UR  - <Go to ISI:>//WOS:001445799800106
DO  - DOI:10.1109/ICECS61496.2024.10848936
UR  - https://juser.fz-juelich.de/record/1038834
ER  -