% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@INPROCEEDINGS{Zhao:1038834,
      author       = {Zhao, Wei and Kuriakose, Neethu and Kusuma, Sabitha and
                      Ammari, Abdelaziz and Ashok, Arun and Grewing, Christian and
                      Zambanini, André and Van Waasen, Stefan},
      title        = {{O}n-{C}hip {A}dvanced {C}ontrol {A}lgorithm for
                      {M}emristor {O}perations with {I}ntegrated {RISC}-{V}
                      {C}ore},
      address      = {Nancy},
      publisher    = {IEEE},
      reportid     = {FZJ-2025-01656},
      isbn         = {979-8-3503-7720-0},
      pages        = {1-4},
      year         = {2024},
      comment      = {2024 31st IEEE International Conference on Electronics,
                      Circuits and Systems (ICECS) : [Proceedings] - IEEE, 2024. -
                      ISBN 979-8-3503-7720-0 -
                      doi:10.1109/ICECS61496.2024.10848936},
      booktitle     = {2024 31st IEEE International
                       Conference on Electronics, Circuits and
                       Systems (ICECS) : [Proceedings] - IEEE,
                       2024. - ISBN 979-8-3503-7720-0 -
                       doi:10.1109/ICECS61496.2024.10848936},
      abstract     = {Advancements in memory technology havepositioned memristors
                      at the forefront of non-volatile memoryapplications,
                      necessitating precise control mechanisms toaccurately
                      program memristor cells to their respective states.This
                      study delves into the utilization of a RISC-V processor
                      andPWM generators to configure registers for analog
                      conductancecontrol of crossbar memristor array architecture
                      for accuratevoltage and current mode operations. The core
                      contribution isthe development of a flexible and efficient
                      control algorithmspecifically designed for RISC-V. A
                      Universal VerificationMethodology Framework (UVMF) testbench
                      is employedto validate control signals, ensuring their
                      accuracy priorto hardware implementation. Results indicate
                      significantenhancements in control efficiency, underlining
                      the potential forintegrating RISC-V with memristor
                      technology.},
      month         = {Nov},
      date          = {2024-11-18},
      organization  = {31st IEEE International Conference on
                       Electronics, Circuits and Systems
                       (ICECS), Nancy (France), 18 Nov 2024 -
                       20 Nov 2024},
      cin          = {PGI-4 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-4-20110106 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:001445799800106},
      doi          = {10.1109/ICECS61496.2024.10848936},
      url          = {https://juser.fz-juelich.de/record/1038834},
}