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| 001 | 1038834 | ||
| 005 | 20250414120447.0 | ||
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| 037 | _ | _ | |a FZJ-2025-01656 |
| 100 | 1 | _ | |a Zhao, Wei |0 P:(DE-Juel1)203161 |b 0 |
| 111 | 2 | _ | |a 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) |g ICECS'24 |c Nancy |d 2024-11-18 - 2024-11-20 |w France |
| 245 | _ | _ | |a On-Chip Advanced Control Algorithm for Memristor Operations with Integrated RISC-V Core |
| 260 | _ | _ | |a Nancy |c 2024 |b IEEE |
| 295 | 1 | 0 | |a 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) : [Proceedings] - IEEE, 2024. - ISBN 979-8-3503-7720-0 - doi:10.1109/ICECS61496.2024.10848936 |
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| 520 | _ | _ | |a Advancements in memory technology havepositioned memristors at the forefront of non-volatile memoryapplications, necessitating precise control mechanisms toaccurately program memristor cells to their respective states.This study delves into the utilization of a RISC-V processor andPWM generators to configure registers for analog conductancecontrol of crossbar memristor array architecture for accuratevoltage and current mode operations. The core contribution isthe development of a flexible and efficient control algorithmspecifically designed for RISC-V. A Universal VerificationMethodology Framework (UVMF) testbench is employedto validate control signals, ensuring their accuracy priorto hardware implementation. Results indicate significantenhancements in control efficiency, underlining the potential forintegrating RISC-V with memristor technology. |
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| 770 | _ | _ | |a IEEE International Conference on Electronics, Circuits and Systems (ICECS) |z 979-8-3503-7720-0 |
| 773 | _ | _ | |a 10.1109/ICECS61496.2024.10848936 |p 1-4 |y 2024 |
| 856 | 4 | _ | |u https://ieeexplore.ieee.org/abstract/document/10848936 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1038834/files/Internal%20Post-Print.pdf |y Restricted |
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