Contribution to a conference proceedings/Journal Article

FZJ-2025-01705

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories

Yu, J.FZJ* ; Manea, P.FZJ* ; Hizzani, M.FZJ* ; Ameli Kalkhouran, S.FZJ* ; Strachan, J. P.FZJ*

2024
IEEE

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Please use a persistent id in citations: doi:10.1109/ICECS61496.2024.10848806

Abstract: In the emerging realm such as in-memory computing and associative memories, the application of memristors necessitates the development of high-performance programming circuits for effective weight updates. The conventional Program-Verify (PV) method requires complex memory peripherals and data converters, which is a major bottleneck for area and power efficiency. Moreover, memristor variability critically undermines the efficacy of AI applications utilizing memristive technology. Addressing these challenges, this paper introduces a novel analog memristor programming circuit that takes memristor variations into account. Leveraging the TSMC 28nm process PDK and the JART VCM vlb var memristor model for simulations, our circuit achieves ±1 µS error margin for over 98.5% of programming results without using ADCs. When contrasted with preceding studies, the proposed solution not only reduces the programming settling time by 15.0% to 87.5% but also exhibits comparable performance to the PV method designed with the same semiconductor and memristor technology.

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Contributing Institute(s):

1. Neuromorphic Compute Nodes (PGI-14)

Research Program(s):

1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)
2. 5233 - Memristive Materials and Devices (POF4-523) (POF4-523)

Appears in the scientific report 2024

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