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001039470 005__ 20250414120449.0
001039470 0247_ $$2doi$$a10.1109/ICECS61496.2024.10848531
001039470 0247_ $$2WOS$$aWOS:001445799800001
001039470 037__ $$aFZJ-2025-01764
001039470 041__ $$aEnglish
001039470 1001_ $$0P:(DE-Juel1)201575$$aShamookh, M.$$b0$$eCorresponding author$$ufzj
001039470 1112_ $$a2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)$$cNancy$$d2024-11-18 - 2024-11-20$$wFrance
001039470 245__ $$aDesign Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS
001039470 260__ $$bIEEE$$c2024
001039470 300__ $$a-
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001039470 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1739459324_4289
001039470 520__ $$aThe process of electroforming (EF) a memristor involves setting the channel resistance via current compliance Icc. This EF phase varies in duration based on the EF voltage VEF, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, Icc, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to 200μA, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems.
001039470 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001039470 536__ $$0G:(DE-82)BMBF-16ME0398K$$aBMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K)$$cBMBF-16ME0398K$$x1
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001039470 7001_ $$0P:(DE-Juel1)176328$$aAshok, A.$$b1$$ufzj
001039470 7001_ $$0P:(DE-Juel1)145837$$aZambanini, A.$$b2$$ufzj
001039470 7001_ $$0P:(DE-HGF)0$$aGelaschus, A.$$b3
001039470 7001_ $$0P:(DE-Juel1)159350$$aGrewing, C.$$b4$$ufzj
001039470 7001_ $$0P:(DE-Juel1)157745$$aBahr, A.$$b5
001039470 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, S.$$b6$$ufzj
001039470 773__ $$a10.1109/ICECS61496.2024.10848531$$y2024
001039470 8564_ $$uhttps://ieeexplore.ieee.org/abstract/document/10848531
001039470 8564_ $$uhttps://juser.fz-juelich.de/record/1039470/files/Post%20Print.pdf$$yRestricted
001039470 909CO $$ooai:juser.fz-juelich.de:1039470$$pVDB
001039470 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)201575$$aForschungszentrum Jülich$$b0$$kFZJ
001039470 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176328$$aForschungszentrum Jülich$$b1$$kFZJ
001039470 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)145837$$aForschungszentrum Jülich$$b2$$kFZJ
001039470 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)159350$$aForschungszentrum Jülich$$b4$$kFZJ
001039470 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142562$$aForschungszentrum Jülich$$b6$$kFZJ
001039470 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001039470 9141_ $$y2024
001039470 920__ $$lyes
001039470 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
001039470 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x1
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