Contribution to a conference proceedings

FZJ-2025-01764

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Design Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS

Shamookh, M. (Corresponding author)FZJ* ; Ashok, A.FZJ* ; Zambanini, A.FZJ* ; Gelaschus, A. ; Grewing, C.FZJ* ; Bahr, A. ; van Waasen, S.FZJ*

2024
IEEE

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Please use a persistent id in citations: doi:10.1109/ICECS61496.2024.10848531

Abstract: The process of electroforming (EF) a memristor involves setting the channel resistance via current compliance Icc. This EF phase varies in duration based on the EF voltage VEF, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, Icc, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to 200μA, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems.

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Contributing Institute(s):

1. Integrated Computing Architectures (PGI-4)
2. Zentralinstitut für Elektronik (ZEA-2)

Research Program(s):

1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)
2. BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) (BMBF-16ME0398K)

Appears in the scientific report 2024

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