TY  - CONF
AU  - Shamookh, M.
AU  - Ashok, A.
AU  - Zambanini, A.
AU  - Gelaschus, A.
AU  - Grewing, C.
AU  - Bahr, A.
AU  - van Waasen, S.
TI  - Design Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS
PB  - IEEE
M1  - FZJ-2025-01764
SP  - -
PY  - 2024
AB  - The process of electroforming (EF) a memristor involves setting the channel resistance via current compliance Icc. This EF phase varies in duration based on the EF voltage VEF, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, Icc, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to 200μA, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems.
T2  - 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
CY  - 18 Nov 2024 - 20 Nov 2024, Nancy (France)
Y2  - 18 Nov 2024 - 20 Nov 2024
M2  - Nancy, France
LB  - PUB:(DE-HGF)8
UR  - <Go to ISI:>//WOS:001445799800001
DO  - DOI:10.1109/ICECS61496.2024.10848531
UR  - https://juser.fz-juelich.de/record/1039470
ER  -