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@INPROCEEDINGS{Shamookh:1039470,
      author       = {Shamookh, M. and Ashok, A. and Zambanini, A. and Gelaschus,
                      A. and Grewing, C. and Bahr, A. and van Waasen, S.},
      title        = {{D}esign {O}ptimization of {H}igh {V}oltage {G}eneration
                      for {M}emristor {E}lectroforming in 28nm {CMOS}},
      publisher    = {IEEE},
      reportid     = {FZJ-2025-01764},
      pages        = {-},
      year         = {2024},
      abstract     = {The process of electroforming (EF) a memristor involves
                      setting the channel resistance via current compliance Icc.
                      This EF phase varies in duration based on the EF voltage
                      VEF, requiring high voltage (HV) as a trade-off with EF
                      time. To achieve CMOS-memristor scalable co-integration,
                      on-chip HV-generation is essential. This study presents an
                      analytical design approach for a proposed three-stage charge
                      pump (CP), focusing on achieving optimal balance among
                      efficiency, output ripple, Icc, and minimal capacitor. The
                      proposed 28 nm three-stage CP requires 1.8 V IO devices for
                      3.35 V output voltage and achieves $46.5\%$ voltage
                      conversion ratio (VCR). It includes a ripple reduction stage
                      to ensure a ripple below 6mV with high current demands of up
                      to 200μA, without an additional space for over-voltage
                      protection within the CP core. Corners and Monte Carlo
                      simulations are conducted to validate the robustness of the
                      design. By eliminating HV-transistors or multi-phase clocks,
                      the design effectively reduces system costs, enhancing the
                      efficiency and scalability of emerging neuromorphic
                      systems.},
      month         = {Nov},
      date          = {2024-11-18},
      organization  = {2024 31st IEEE International
                       Conference on Electronics, Circuits and
                       Systems (ICECS), Nancy (France), 18 Nov
                       2024 - 20 Nov 2024},
      cin          = {PGI-4 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-4-20110106 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)8},
      UT           = {WOS:001445799800001},
      doi          = {10.1109/ICECS61496.2024.10848531},
      url          = {https://juser.fz-juelich.de/record/1039470},
}