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| Home > Publications database > Design Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS > print |
| 001 | 1039470 | ||
| 005 | 20250414120449.0 | ||
| 024 | 7 | _ | |a 10.1109/ICECS61496.2024.10848531 |2 doi |
| 024 | 7 | _ | |a WOS:001445799800001 |2 WOS |
| 037 | _ | _ | |a FZJ-2025-01764 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Shamookh, M. |0 P:(DE-Juel1)201575 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) |c Nancy |d 2024-11-18 - 2024-11-20 |w France |
| 245 | _ | _ | |a Design Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS |
| 260 | _ | _ | |c 2024 |b IEEE |
| 300 | _ | _ | |a - |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
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| 520 | _ | _ | |a The process of electroforming (EF) a memristor involves setting the channel resistance via current compliance Icc. This EF phase varies in duration based on the EF voltage VEF, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, Icc, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to 200μA, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems. |
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| 700 | 1 | _ | |a Ashok, A. |0 P:(DE-Juel1)176328 |b 1 |u fzj |
| 700 | 1 | _ | |a Zambanini, A. |0 P:(DE-Juel1)145837 |b 2 |u fzj |
| 700 | 1 | _ | |a Gelaschus, A. |0 P:(DE-HGF)0 |b 3 |
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| 700 | 1 | _ | |a van Waasen, S. |0 P:(DE-Juel1)142562 |b 6 |u fzj |
| 773 | _ | _ | |a 10.1109/ICECS61496.2024.10848531 |y 2024 |
| 856 | 4 | _ | |u https://ieeexplore.ieee.org/abstract/document/10848531 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1039470/files/Post%20Print.pdf |y Restricted |
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| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-523 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Neuromorphic Computing and Network Dynamics |9 G:(DE-HGF)POF4-5234 |x 0 |
| 914 | 1 | _ | |y 2024 |
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| 920 | 1 | _ | |0 I:(DE-Juel1)PGI-4-20110106 |k PGI-4 |l Integrated Computing Architectures |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)ZEA-2-20090406 |k ZEA-2 |l Zentralinstitut für Elektronik |x 1 |
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