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| Hauptseite > Publikationsdatenbank > Cryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel |
| Hauptseite > Publikationsdatenbank > Cryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel |
| Contribution to a conference proceedings | FZJ-2025-04447 |
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2025
IEEE
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Please use a persistent id in citations: doi:10.1109/ESSERC66193.2025.11214120
Abstract: We investigate the cryogenic performance of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors, focusing on devices featuring counter-doped channels. We explore counterdoping as a potential strategy to mitigate the increased threshold voltage at cryogenic temperatures, aiming to reduce power consumption. We extract key performance metrics such as threshold voltage, subthreshold swing, and other relevant parameters from cryogenic measurements, and compare them against conventional FD-SOI devices. Our results demonstrate that counter-doping enables effective threshold voltage control without compromising electrical performance, positioning it as a promising solution for ultra-low-power cryogenic CMOS optimization in scalable quantum computing applications.
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