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001     1050048
005     20251219155103.0
024 7 _ |a arXiv:2505.10248
|2 arXiv
037 _ _ |a FZJ-2025-05762
088 _ _ |a arXiv:2505.10248
|2 arXiv
100 1 _ |a Salwa, Yasmeen Neyaz
|0 P:(DE-Juel1)188965
|b 0
|e Corresponding author
|u fzj
245 _ _ |a Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity
260 _ _ |c 2025
336 7 _ |a Preprint
|b preprint
|m preprint
|0 PUB:(DE-HGF)25
|s 1766155727_16742
|2 PUB:(DE-HGF)
336 7 _ |a WORKING_PAPER
|2 ORCID
336 7 _ |a Electronic Article
|0 28
|2 EndNote
336 7 _ |a preprint
|2 DRIVER
336 7 _ |a ARTICLE
|2 BibTeX
336 7 _ |a Output Types/Working Paper
|2 DataCite
520 _ _ |a Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research.
536 _ _ |a 5234 - Emerging NC Architectures (POF4-523)
|0 G:(DE-HGF)POF4-5234
|c POF4-523
|f POF IV
|x 0
588 _ _ |a Dataset connected to DataCite
700 1 _ |a Ashok, A.
|0 P:(DE-Juel1)176328
|b 1
|u fzj
700 1 _ |a Schiek, Michael
|0 P:(DE-Juel1)133935
|b 2
|u fzj
700 1 _ |a Grewing, C.
|0 P:(DE-Juel1)159350
|b 3
|u fzj
700 1 _ |a Zambanini, A.
|0 P:(DE-Juel1)145837
|b 4
|u fzj
700 1 _ |a van Waasen, S.
|0 P:(DE-Juel1)142562
|b 5
|u fzj
856 4 _ |u https://arxiv.org/abs/2505.10248
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 0
|6 P:(DE-Juel1)188965
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 1
|6 P:(DE-Juel1)176328
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 2
|6 P:(DE-Juel1)133935
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 3
|6 P:(DE-Juel1)159350
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 4
|6 P:(DE-Juel1)145837
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 5
|6 P:(DE-Juel1)142562
913 1 _ |a DE-HGF
|b Key Technologies
|l Natural, Artificial and Cognitive Information Processing
|1 G:(DE-HGF)POF4-520
|0 G:(DE-HGF)POF4-523
|3 G:(DE-HGF)POF4
|2 G:(DE-HGF)POF4-500
|4 G:(DE-HGF)POF
|v Neuromorphic Computing and Network Dynamics
|9 G:(DE-HGF)POF4-5234
|x 0
920 _ _ |l yes
920 1 _ |0 I:(DE-Juel1)PGI-4-20110106
|k PGI-4
|l Integrated Computing Architectures
|x 0
980 _ _ |a preprint
980 _ _ |a EDITORS
980 _ _ |a VDBINPRINT
980 _ _ |a I:(DE-Juel1)PGI-4-20110106
980 _ _ |a UNRESTRICTED

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